ZEN2/ZEN3 MTS/VMR全系 32 B read + 16 B write per fclk, GMI gen2
ZEN4 RPH AM5 维持不变，32 B read + 16 B write per fclk, GMI gen3
Gen2到Gen3带宽翻倍，但是bandwidth维持不变其实就是砍通道了
Like Zen 2 and Zen 3, each Zen 4 core complex has a 32B/cycle read link from fabric, and a 16B/cycle write link. Last article, we noted that write bandwidth to DDR5-6000 was likely limited by the 16B/cycle links from the two CCDs. We see a similar read bandwidth limitation from one CCD. We ran our memory bandwidth test with the 3 GB test size and scaled thread counts to hit all physical cores. CCXes and CCDs were filled one before another. On the 3950X, that meant filling both CCXes on a CCD first. From the results, we see clear signs that a single 7950X CCD is restricted by its 32B/cycle link to fabric.
https://chipsandcheese.com/2023/ ... vel-stuff-and-igpu/ |
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发表于 2024-5-20 05:07
